OAM is separate from VRAM and is located inside the SOC.
The PPU is clocked at 4mhz and I suspect OAM is also clocked at 4mhz (though it could also be implemented as two banks clocked at 2mhz with status in one bank and y location in the other bank). So 4 reads per CPU cycle sounds correct.
The PPU is clocked at 4mhz and I suspect OAM is also clocked at 4mhz (though it could also be implemented as two banks clocked at 2mhz with status in one bank and y location in the other bank). So 4 reads per CPU cycle sounds correct.