The chip never did such operations... instead they ran it as both a secondary processor and a math DSP. The operations otherwise were entirely software, and conventional.
Another interesting one was the SA-1 chip used in a few games, such as Super Mario RPG. Its a SNES-compatible 65C816 that is 3x faster, has its own RAM bank, and can interrupt and be interrupt the main CPU, among other features, and was used to offload a lot of things, including some graphics tasks.
For X86 at least, there's different names for the same instruction, depending on what you want to do. So this could be an instruction that has other more general uses.
That said, digging around I havent found reference to Intel using the chip, and another responder claims it was a different chip by the same manufacturer.
Intel used ARC CPUs in the Intel ME before Skylake, a several generations descendant of the one designed by Argonaut. Its used a few other places in IoT-land as well. ARC is a well understood architecture that is easy to modify for individual customers, and can be fabbed anywhere.
Another interesting CPU that made its way around was the family that the SPC700 (SNES) and SPC1000 (PS1) audio DSPs belong to. They've shown up in a few embedded devices that needed to do audio work, such inside of AVRs and other similar devices.
SuperFX is a CISC. Byte opcodes with prefixes, complex memory access instructions, two address, etc.
ARCompact is a RISC. 32-bit instructions with a 16-bit subset that expands to what you could encode with the 32-bit, fairly simple load store arch, three address ops, huge register file, etc.
They're about as different as two archs can get; they're just made by the same people.
The best quote, from Jez San, one of Argonaut's founders, is, "At the time that it came out, it was also the world's best-selling RISC microprocessor until ARM became standardised in every cellphone and took the market by storm."
ARV32, RISC-V, PowerPC, ARM's Thumb, all variable instruction encoding. The SuperFX came out after the Pentium, the first consumer super-scalar pipelined CISC CPU, and not the first CISC to do it.
None of those are byte opcodes encoding with prefixes.
None of those are variable width depending on what type of argument you have.
Also, PowerPC isn't even variable width at all.
And the Pentium was the first pipelined CISC microprocessor, ie. a single chip. At the time there was a holy war going on with one side being of the opinion that you shouldn't pipeline single chip processors, but instead rely on Moore's law. The thought was that the mainframe style multichip modules needed a pipeline to account for off chip delays, but that all on the same die it was unnecessary and created too unpredictability with pipeline bubbles, etc. Those people were obviously wrong and lost.
Edit: also the Pentium was released a month after StarFox was looking into it. And when you account for the long lead times of hardware, their statements make sense timeline wise. Particularly when you consider that that RISC was a huge buzzword at the time and being misapplied, sort of like how now everybody doing a simple linear regression is talking about all the machine learning they're doing.
The plot pixel instruction was a 'write to SNES's custom tile/attribute format as if it were a linear framebuffer' instruction. Pretty difficult to use generally.
Another interesting one was the SA-1 chip used in a few games, such as Super Mario RPG. Its a SNES-compatible 65C816 that is 3x faster, has its own RAM bank, and can interrupt and be interrupt the main CPU, among other features, and was used to offload a lot of things, including some graphics tasks.