I checked https://en.wikipedia.org/wiki/7400-series_integrated_circuit... and gate delay (tpd) for 74HC is 15 ns.

I wouldn't expect more than 1 MIPS, which is what the DEC VAX 11/780 was doing around 1980.

(Awesome one-man project, if that's the case.)

If it gets 1 MIPS I'd be absolutely amazed, check out the size of the wire wrap boards:

http://www.sol-1.org/images/sol/board-1.jpg

They're normal sized boards fwiw.

I didn't mean to imply that they are abnormal, just that they are large and large boards like that tend to be harder to make stable when using wire wrap as a technique. I've done this - and stacks of them too - but I've also spent days tracing a faulty wire, and the chance of such faults goes up as the number of wires goes up.

Those are Multibus-1 prototyping boards, so they'd be 12"x6.75". It's a good size for building non-trivial things.

Wire length matching would seem to be a big factor in attaining the highest performance.