If you're already familiar with arm64 assembly language then just read the RISC-V ISA manual. It's short and simple.

https://riscv.org/technical/specifications/

riscv64 Linux syscall numbers are the same as arm64 ones. Just put the syscall number into `a7` instead of `x8`. And args in `a0`..`a3`, obv. Use `ecall` instead of `svc 0`. Boom!

i'm probably not a good person to give advice on this, but what i've been doing is installing the cross-compilation gcc environment under debian and qemu-user. this allows me to build statically linked executables and run them as if they were native executables, and also to disassemble the executables and object files with riscv64-linux-gnu-objdump (though it produces incorrect output for instructions like addi and slli, it's good enough to see what's going on)

specifically i installed gcc-riscv64-linux-gnu and qemu-user-binfmt

also i read the risc-v spec and assembly programming manual

i also got some risc-v single-board computers but haven't done anything with them yet

i haven't been doing anything with the v extension, which i think is the most widely supported simd-like extension; though it's not exactly simd, it offers the same kinds of benefits for the same kinds of applications

> riscv64-linux-gnu-objdump (though it produces incorrect output for instructions like addi and slli

The assembler accepts either syntax:

    user@starfive:~$ echo add a0,a0,13 \; addi a1,a1,420 | as
    user@starfive:~$ objdump -d a.out
    
    a.out:     file format elf64-littleriscv
    
    
    Disassembly of section .text:
    
    0000000000000000 <.text>:
       0:   00d50513                add     a0,a0,13
       4:   1a458593                add     a1,a1,420

Also, objdump will print them as `addi` if you give the `-Mno-aliases` option.

yeah, i know it accepts it, but that doesn't make it right ;)

thanks for the tip about no-aliases! i had no idea. i don't suppose there's an option to allow me to write arm-ual-style `add a1, a0` instead of `c.add a1, a0` or `add a1, a1, a0`, is there? because in the first case i can't assemble it without rvc, and the second case is annoying

i guess i should write my own assembler instead of whining

Edit: sorry I missread, I though you were just interested in the vector extension (SIMD)

for the genral assembly there isn't mutch to learn tbh, look at the isa reference card and maybe also look at the B (bit manipulation) extension: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...

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Here are some resources on RVV I can recommend:

RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...

RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer

Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U

RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...

If you want to see a more complex example/real world application, then you might also be interested in my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...

In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).