All of which are completely irrelevant implementation details hidden behind the ISA. The x86-64 ISA promises execution of instructions in the specified order, a certain number of registers, etc. and that's all they need to know.
The claim is that learning assembler first will build a better intuition about the inner workings, and thus performance, of the processor.
The reality is that any assembler simple enough to be taught as your first contact with programming will leave you with a wrong intuition about how modern processors work, and thus a wrong intuition about the relative performance of various operations.
Having no intuition about something is better than building a bad intuition, especially at the beginning of your learning journey.
> The x86-64 ISA promises execution of instructions in the specified order
It doesn’t, and out-of-order CPUs don’t do that. https://en.wikipedia.org/wiki/Out-of-order_execution: “In this paradigm, a processor executes instructions in an order governed by the availability of input data and execution units, rather than by their original order in a program.”
Out-of-order execution is an internal optimization, from the outside results are still guaranteed to be available in order - e.g. the instruction stream appears to be executed in order when observing the CPU from the outside.
For instance you don't need to be afraid that an instruction uses garbage inputs just because a previous instruction hadn't finished computing an input value to the instruction. At worst you'll get a pipeline stall if the CPU can't fill the gap with out-of-order executed instructions.
On some CPUs it does get tricky once memory is involved though (on ARM, but not on x86).
> from the outside results are still guaranteed to be available in order - e.g. the instruction stream appears to be executed in order when observing the CPU from the outside.
> […]
> On some CPUs it does get tricky once memory is involved though (on ARM, but not on x86).
“Among the commonly used architectures, x86-64 processors have the strongest memory order, but may still defer memory store instructions until after memory load instructions.”
