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The on-die ECC used by DDR5 (and pretty much all other recent DRAM) actually doesn't have many compatibility implications, precisely because it's done entirely on-die unlike traditional ECC memory modules that include an extra one or two chips to enable end to end ECC managed by the CPU's memory controller.

The more significant incompatibilities between DDR4 and DDR5 are in the power delivery (DDR5 has voltage regulators on the module rather than on the motherboard) and rearranging of the address bus and command encoding.



Oh, right, yeah I see the meta-confusion. They are incompatible for a bunch of reasons, of which ECC is not particularly relevant.




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