The advantage of this method of programming is that complex parallel processing tasks can be reduced to a directed acyclic graph from information sources, through filters, and into information sinks. You can then take this graph and either interpret it by creating threads for each of the nodes in the graph and shuffling information between them using FIFO queues, or try to compile the graph to a better performing, but "flattened" native program.
The main problems with this approach are how to properly represent timing, latency, and node state, since you can send one piece of information through the graph at a time, or you can try to improve efficiency by pipelining the graph - using the graph like a shift register, and making sure every node has work to do at all times.
Of course it's not a cure-all solution and doesn't map well to every problem domain, but it is generally easier to reason about for complex parallel processing tasks, and can be deployed over multiple machines with minimal "glue" code.
So, hardware description languages, which are essentially flow-based programming languages, solve this using clocks and sensitivity lists. An FBPL for web programming would probably use events instead of edge/level triggers and timers instead of clocks.
The main problems with this approach are how to properly represent timing, latency, and node state, since you can send one piece of information through the graph at a time, or you can try to improve efficiency by pipelining the graph - using the graph like a shift register, and making sure every node has work to do at all times.
Of course it's not a cure-all solution and doesn't map well to every problem domain, but it is generally easier to reason about for complex parallel processing tasks, and can be deployed over multiple machines with minimal "glue" code.